1. Field of the Invention
This invention relates to a semiconductor memory device and a control method for the semiconductor memory device. More particularly, this invention relates to a nonvolatile semiconductor memory device including MOS transistors, each having a floating gate and a control gate.
2. Description of the Related Art
NOR and NAND flash memories have been widely used as nonvolatile semiconductor memories.
In recent years, a flash memory combining the features of both the NOR and the NAND flash memory has been proposed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. A flash memory of this type has memory cells, each including two MOS transistors (hereinafter, referred to as a 2Tr flash memory).
In the flash memory, to write or erase data, a voltage higher than one from an external power supply is applied to between a word line and a semiconductor substrate (or a drain of a memory cell). Once the data write or erase operation is completed, the potential of a control gate and the semiconductor substrate are reset to, for example, 0V (this is called a reset operation).
However, in the conventional flash memory, a parasitic capacitance is present between the control gate and the semiconductor substrate. Consequently, coupling caused by the parasitic capacitance disadvantageously makes it difficult to perform a quick reset operation.